A Configurable System-on-Chip (CSoC) is a single-chip combination of an industry-standard microprocessor, embedded programmable logic, memory and a dedicated system bus. In addition to the processor, the CSoC may incorporate many dedicated system features including a cache memory, an external memory interface unit, and a direct memory access (DMA) controller. These features are integrated with a dedicated configurable system interconnect (CSI) bus and embedded field programmable logic array (FPGA). This FPGA is also referred to as configurable system logic or CSL.
FIG. 1 is a block diagram illustrating an example of a prior art configurable system-on-chip (CSoC). The CSoC includes a CSL 110, a DMA controller 125, a central processing unit (CPU) 105, a memory 130 and a CSI bus 100. The DMA controller 125 may have multiple DMA channels (e.g., four). Each of the DMA channels can be programmed independently and any one of the channels may be active at any moment. Programming the DMA channels may involve writing into appropriate DMA registers.
The CPU 105 or the DMA controller 125 can master the CSI bus 100 while the CSL 110 cannot. When a signal is asserted for a particular DMA channel, the DMA controller 125 asks an arbiter 140 to grant it the CSI bus 100 so that the DMA controller 125 can use the CSI bus 100. The DMA controller 125 may request for control of the CSI bus 100 by asserting request signal which goes to the arbiter 140. Typically, the CSI bus 100 is a 32-bit address bus that is used to selectively access various components of the internal circuitry (e.g., registers in the CSL, DMA controllers, Ethernet controller, etc.) or external devices (e.g., memory devices, etc.).
Generally, there are bus signals driven to the CSL 110 containing addresses and write data, and there are bus signals coming from the CSL 110 containing read data. Although the CSL 110 is capable of providing data, it is not capable of specifying addresses, direction of data, or transaction size. The CSL 110 can send or receive data through transactions with the DMA controller 125. The DMA controller 125 acts as the bus master of the CSI bus 100. Similarly, the DMA controller 125 may participate in the data transfer between the memory 130 and other devices 135, and between areas of the memory 130.
The CSL 110 may include multiple soft modules or CSL devices 115, 117. The CSL 110 also includes CSL bus signal lines for outgoing and incoming signals. For example, the CSL 110 may include two outgoing point-to-point bus signal lines (not shown) and two incoming point-to-point bus signal lines (not shown). These bus signal lines carry bus signals between the CSL devices 115, 117, and the DMA controller 125. The DMA controller 125 has registers to store the number of bytes to be transferred and the 32-bit starting address in memory, or a 32-bit destination address, or both source and destination addresses for memory to memory transfers. The DMA controller 125 can transfer the bytes one at a time under control of a DMA request signal, or a single request can initiate the transfer of an entire block of data. Once a transfer is completed, the DMA controller 125 may shut down until it is needed again.
Many network protocols (e.g., Ethernet, USB, etc.) are packet (or frame) based. This requires that a device attempting to implement one of these protocols determine packet boundaries from the transmit data stream and provide packet boundary information for the receive data stream. Other information contained in the transmit data stream and receive data stream may include transmit options, receive status, transfer priority, etc. They are referred to collectively as metadata. The metadata may be placed contiguous with the data. Placing the metadata contiguous with the data is possible in a normal implementation, but causes software problems. So called “zero-copy” protocol stacks are more efficient because the data to be sent or received is placed in memory by the producer (e.g., CSL device) and is left there for subsequent processing. However, for transmit using a zero-copy stack, it is infeasible to add the metadata contiguous with the normal data since this would require expanding the allocation of a memory block that has already been allocated. This is something that most memory allocation schemes cannot do. Placing control information in the midst of data presents difficulties to software.